Texas Instruments 8607701CA
Image is only for reference
| Attribute | Value |
|---|---|
| HTS | 8542.39.00.90 |
| PPAP | No |
| SVHC | Yes |
| EU RoHS | Not Compliant |
| Mounting | Through Hole |
| ECCN (US) | EAR99 |
| Packaging | Tube |
| Pin Count | 14 |
| Automotive | No |
| Lead Shape | Through Hole |
| PCB changed | 14 |
| Availability | No Stock Available |
| Logic Family | HC |
| Package Width | 7.19(Max) |
| Logic Function | Parity Generator/Checker |
| Number of Bits | 9 |
| Package Height | 3.56(Max) |
| Package Length | 19.94(Max) |
| Supplier Package | CDIP |
| Standard Package Name | DIP |
| Manufacturer Lead Time | 26 weeks |
| SVHC Exceeds Threshold | Yes |
| Supplier Temperature Grade | Military |
| Number of Elements per Chip | 1 |
| Maximum Quiescent Current (uA) | 8 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -55 |
| Absolute Propagation Delay Time (ns) | 300 |
| Maximum Operating Supply Voltage (V) | 6 |
| Minimum Operating Supply Voltage (V) | 2 |
| Typical Operating Supply Voltage (V) | 2.5|3.3|5 |
| Maximum Low Level Output Current (mA) | 5.2 |
| Maximum High Level Output Current (mA) | -5.2 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 200@2V|[email protected]|34@6V |
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Packaging Process
