Microchip Technology A3PN010-2QNG48
Image is only for reference
| Attribute | Value |
|---|---|
| HTS | 8542.31.00.60 |
| PPAP | No |
| EU RoHS | Compliant |
| Mounting | Surface Mount |
| ECCN (US) | EAR99 |
| Packaging | Tray |
| Pin Count | 48 |
| Tradename | ProASIC |
| User I/Os | 34 |
| Automotive | No |
| Lead Shape | No Lead |
| Family Name | ProASIC®3 nano |
| PCB changed | 48 |
| Speed Grade | 2 |
| Availability | No Stock Available |
| Package Width | 6 |
| Package Height | 0.88 |
| Package Length | 6 |
| Copy Protection | No |
| I/O Voltage (V) | 1.5|1.8|2.5|3.3 |
| Programmability | Yes |
| Supplier Package | QFN EP |
| Device Logic Gates | 10000 |
| Process Technology | 130nm |
| Device System Gates | 10000 |
| Number of I/O Banks | 2 |
| Number of Registers | 260 |
| Program Memory Type | Flash |
| Standard Package Name | QFN |
| Number of Global Clocks | 4 |
| In-System Programmability | Yes |
| Reprogrammability Support | Yes |
| Supplier Temperature Grade | Commercial |
| Operating Supply Voltage (V) | 1.5 |
| Number of Inter Dielectric Layers | 7 |
| Maximum Operating Temperature (°C) | 85 |
| Minimum Operating Temperature (°C) | -20 |
| Maximum Operating Supply Voltage (V) | 1.575 |
| Minimum Operating Supply Voltage (V) | 1.425 |
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Packaging Process
