Efficient Power Conversion Corporation EPC2106
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Manufacturer
Manufacturer No
EPC2106
Availability
In Stock
Package
Die
Packaging
Tape and Reel
Description
Trans MOSFET N-CH GaN 100V 1.7A 9-Pin Die T/R
Datasheet
Payment
Delivery
HTS
EA
PPAP
Unknown
EU RoHS
Compliant
Category
Power MOSFET
Material
GaN
Mounting
Surface Mount
ECCN (US)
EAR99
Packaging
Tape and Reel
Pin Count
9
Automotive
Unknown
PCB changed
9
Availability
No Stock Available
Channel Mode
Enhancement
Channel Type
N
Configuration
Dual
Package Width
1.35
Package Height
0.63
Package Length
1.35
Supplier Package
Die
Maximum IDSS (uA)
250
Number of Elements per Chip
2
Typical Gate Charge @ Vgs (nC)
0.73@5V@Q1|0.76@5V@Q2
Maximum Gate-Source Voltage (V)
6
Typical Output Capacitance (pF)
52@Q1|61@Q2
Maximum Drain-Source Voltage (V)
100
Typical Gate Plateau Voltage (V)
2.4
Typical Diode Forward Voltage (V)
2.1
Typical Gate to Drain Charge (nC)
0.14
Maximum Gate Threshold Voltage (V)
2.5
Minimum Gate Threshold Voltage (V)
0.8
Typical Gate Threshold Voltage (V)
1.4
Typical Gate to Source Charge (nC)
0.24
Maximum Operating Temperature (°C)
150
Minimum Operating Temperature (°C)
-40
Maximum Continuous Drain Current (A)
1.7
Operating Junction Temperature (°C)
-40 to 150
Typical Input Capacitance @ Vds (pF)
79@50V
Typical Reverse Recovery Charge (nC)
0
Maximum Drain-Source Resistance (mOhm)
70@5V
Maximum Gate-Source Leakage Current (nA)
1000000
Maximum Positive Gate-Source Voltage (V)
6
Maximum Pulsed Drain Current @ TC=25°C (A)
18
Typical Drain-Source Resistance @ 25°C (mOhm)
115@3V|[email protected]|65@4V|[email protected]|55@5V
Typical Reverse Transfer Capacitance @ Vds (pF)
0.5@50V
Maximum Junction Ambient Thermal Resistance on PCB (°C/W)
81(Typ)
| Attribute | Value |
|---|---|
| HTS | EA |
| PPAP | Unknown |
| EU RoHS | Compliant |
| Category | Power MOSFET |
| Material | GaN |
| Mounting | Surface Mount |
| ECCN (US) | EAR99 |
| Packaging | Tape and Reel |
| Pin Count | 9 |
| Automotive | Unknown |
| PCB changed | 9 |
| Availability | No Stock Available |
| Channel Mode | Enhancement |
| Channel Type | N |
| Configuration | Dual |
| Package Width | 1.35 |
| Package Height | 0.63 |
| Package Length | 1.35 |
| Supplier Package | Die |
| Maximum IDSS (uA) | 250 |
| Number of Elements per Chip | 2 |
| Typical Gate Charge @ Vgs (nC) | 0.73@5V@Q1|0.76@5V@Q2 |
| Maximum Gate-Source Voltage (V) | 6 |
| Typical Output Capacitance (pF) | 52@Q1|61@Q2 |
| Maximum Drain-Source Voltage (V) | 100 |
| Typical Gate Plateau Voltage (V) | 2.4 |
| Typical Diode Forward Voltage (V) | 2.1 |
| Typical Gate to Drain Charge (nC) | 0.14 |
| Maximum Gate Threshold Voltage (V) | 2.5 |
| Minimum Gate Threshold Voltage (V) | 0.8 |
| Typical Gate Threshold Voltage (V) | 1.4 |
| Typical Gate to Source Charge (nC) | 0.24 |
| Maximum Operating Temperature (°C) | 150 |
| Minimum Operating Temperature (°C) | -40 |
| Maximum Continuous Drain Current (A) | 1.7 |
| Operating Junction Temperature (°C) | -40 to 150 |
| Typical Input Capacitance @ Vds (pF) | 79@50V |
| Typical Reverse Recovery Charge (nC) | 0 |
| Maximum Drain-Source Resistance (mOhm) | 70@5V |
| Maximum Gate-Source Leakage Current (nA) | 1000000 |
| Maximum Positive Gate-Source Voltage (V) | 6 |
| Maximum Pulsed Drain Current @ TC=25°C (A) | 18 |
| Typical Drain-Source Resistance @ 25°C (mOhm) | 115@3V|[email protected]|65@4V|[email protected]|55@5V |
| Typical Reverse Transfer Capacitance @ Vds (pF) | 0.5@50V |
| Maximum Junction Ambient Thermal Resistance on PCB (°C/W) | 81(Typ) |
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